
PNI Sensor Corporation DOC#1017814 r01
V2Xe User Manual – May 2012 Page 5
4 Set-Up
4.1 Electrical Connections
The V2Xe incorporates two 7-pin SIP connectors. The pin-out is given below in Table 4-1,
where pin #1 and pin #14 are defined in the mechanical drawing (Figure 3-1).
Table 4-1: Pin Descriptions
Serial Clock input for SPI port
Master In, Slave Out for the Module SPI port
Master Out, Slave In for the Module SPI port
Slave Select for the V2Xe’s SPI port. SSN must remain low until the
command response is clocked out.
Reserved I/O. Do not connect.
The SYNC line is not needed except in cases where the V2Xe gets out of
synchronization with the host. Synchronization issues primarily occur
during power-up when I/O and hardware are initialized. This may cause
glitches in the clock line, which can be interpreted by the V2Xe as clock
cycles. A rising edge on the V2Xe SYNC line resets the V2Xe’s SPI and
communication buffers. The SYNC line is asynchronous with respect to
the SPI, so proper care in its implementation is mandatory. Contact PNI if
you are experiencing synchronization issues.
Reserved I/O. Do not connect.
Reserved I/O. Do not connect.
Reserved I/O. Do not connect.
Reserved I/O. Do not connect.
3V regulated supply voltage
After making the electrical connections, it is a good idea to perform some simple tests to
ensure the V2Xe is working as expected. See Section 5 for how to operate the V2Xe using
the V2Xe binary protocol.
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