
PNI Sensor Corporation Doc 1017252 r03
RM3100 & RM2100 Sensor Suite User Manual Page 25 of 45
Table 4-2: SPI Timing Specifications
Setup data before active edge
Hold data after active edge
Clock falling edge to valid data
Final clock cycle falling edge to SSN HIGH
SSN HIGH to output data tri-state
SSN HIGH to LOW (time between transactions)
4.5 I
2
C Requirements
The MagI2C can operate as a slave device on an I
2
C bus. It is identified by a 7-bit slave
address. The higher 5 bits of the slave address are pre-defined in hardware and the same for
all MagI2C devices. PNI has registered these first 5 bits as 0b01000. The lower 2 bits of the
slave address are user-configurable, using pins 3 and 28. As such, 4 different slave addresses
are possible. For example, setting pin 3 HIGH and pin 28 LOW results in an address of
0b0100001.
The MagI2C’s I
2
C interface complies with NXP’s UM10204 specification and user manual,
revision 03. Standard, fast, fast plus, and high speed modes of the I
2
C protocol are
supported. Below is a link to this document.
http://www.nxp.com/documents/user_manual/UM10204.pdf
4.5.1 I
2
C Register Write
A generic Write transaction is given below.
------------ Data Transferred (n bytes + acknowledge) ------------
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